Huawei’s Tau Scaling Bet: A New Route to 1.4nm-Level Chips by 2031 Amid Sanctions

Huawei Technologies unveiled a fresh architectural approach on May 25 that it says will let its high-end chips reach transistor densities equivalent to 1.4-nanometer processes by 2031. The announcement, delivered at a semiconductor symposium in Shanghai, comes as the company and its manufacturing partner SMIC push against years of U.S. export controls that block access to extreme ultraviolet lithography tools.

Call it necessity. Since 2019, when Washington placed Huawei on its entity list, the firm lost reliable access to the most advanced production equipment. Yet its Kirin 9000s chip, built on SMIC’s 7nm-class process and revealed inside the Mate 60 Pro in 2023, proved Beijing could still deliver competitive consumer silicon. Reuters reported that SMIC shares jumped 7.6 percent the day of the latest disclosure.

Now Huawei wants to accelerate. Its semiconductor chief, He Tingbo, introduced the Tau Scaling Law. This principle moves away from simply shrinking transistors. Instead it targets reductions in the time signals and data take to travel through chips and systems. The company paired the concept with an architecture named LogicFolding. Early versions will appear in Kirin smartphone processors launching later this year. By 2030 the same techniques should reach Ascend AI accelerators and even large clusters of hundreds or thousands of chips for data centers.

“By 2031, the high-end chips Huawei designs based on the τ Scaling Law are expected to feature a transistor density that is equivalent to 1.4 nm processes,” the firm stated. TSMC, by comparison, plans to begin volume output of its own 1.4nm technology in 2028. The gap remains roughly three years. Bloomberg noted that Huawei sees its new pathway as a way to shorten that distance without the forbidden tools. Bloomberg detailed He Tingbo’s claim of a breakthrough in making advanced semiconductors absent cutting-edge equipment.

The original 2031 goal first surfaced in earlier coverage. Engadget covered Huawei’s assertion that such densities could become feasible and affordable despite sanctions. Today’s update adds concrete technical claims and nearer-term product milestones. Over the past six years, Huawei says its chip unit has designed and mass-produced 381 chips using principles aligned with Tau Scaling. Those parts serve smartphones, AI computing, and other sectors.

Progress at the foundry level tells a more measured story. SMIC has expanded 7nm output. Industry estimates placed its advanced-node wafer starts near 50,000 per month in 2025, with plans to approach 100,000 for 7nm- and 5nm-class capacity within two years. Tom’s Hardware cited Chinese targets to reach half a million monthly wafers by 2030. Yet yields remain a constraint. Reports from 2025 placed SMIC’s 7nm yields between 20 and 40 percent in some cases, with 5nm pilot runs under way for mass production possibly in 2026. Huawei’s Ascend 910C AI chip already runs on the 7nm node and competes in domestic inference workloads.

Recent analysis shows incremental gains. TechInsights examined the Kirin 9030 in Huawei’s Mate 80 series and found it built on an evolved SMIC process. Bloomberg reported those advances in late 2025. Capacity still falls short of demand. CSIS analysts estimated SMIC targeted 50,000 wafers per month of 7nm by the end of 2025, though real output faced bottlenecks. The CSIS report from March 2025 highlighted low yields and the absence of EUV as persistent hurdles.

LogicFolding addresses some of those limits by shortening internal wiring. The result, Huawei claims, boosts performance without requiring the smallest possible feature sizes. He Hui, director of semiconductor research at Omdia, described the shift as moving from node-driven scaling to system-level efficiency. “Rather than depending solely on smaller transistors, the company is focusing on shortening interconnect, lowering latency and improving data movement inside the chip,” he told Reuters.

But analysts caution against overstatement. Brady Wang of Counterpoint Research pointed to cost, power, heat, and integration challenges, especially for cloud AI servers. “In the short term, China may narrow the gap with global leaders, but a technology gap with the most advanced nodes will still remain,” he said. Huawei’s own He Tingbo acknowledged the difficulties. New design tools will be needed. Overheating risks rise as density climbs from phones to massive clusters. Still he expressed confidence: solutions exist that should keep Huawei competitive in mobile and AI computing over the next decade.

The timing carries weight. Chinese tech giants have rushed to secure Huawei’s Ascend chips after DeepSeek’s V4 model demonstrated strong results on domestic hardware. Revenue from Huawei’s AI processors could exceed $12 billion this year, up more than 60 percent from 2025, according to people familiar with orders. Reuters reported that surge in early May. Nvidia’s CEO Jensen Huang conceded much of the China AI chip market to Huawei earlier this month.

Beijing backs the effort with policy and funding. Its latest five-year plans prioritize advanced logic nodes, yield improvements, and packaging research. SMIC opened an advanced packaging institute in Shanghai in January. Hua Hong, the country’s second-largest foundry, prepares 7nm capacity at a new Shanghai facility, ending SMIC’s temporary monopoly on leading-edge production. Recent analysis from Oplexa noted total Chinese advanced-node capacity could reach 60,000 wafers per month through 2026.

Yet physics and economics impose limits. Multi-patterning with deep ultraviolet lithography works for 7nm and 5nm-class nodes but drives complexity, lower yields, and higher costs. SMIC’s 5nm effort reportedly carries prices 50 percent above TSMC equivalents in some projections. Scaling to true 3nm or below without EUV looks distant. Huawei’s bet therefore rests on architecture, packaging, and clever interconnect design to deliver equivalent real-world gains.

The Tau Scaling announcement fits a pattern. Each Huawei disclosure since the Mate 60 surprise has revealed steady, if costly, forward movement. The firm no longer talks of matching TSMC node for node. It now defines success through system performance, power efficiency, and volume production of domestic AI infrastructure. Whether LogicFolding scales from a few Kirin chips this year to thousands of AI accelerators by decade’s end will decide if the 2031 density target becomes reality or remains aspirational.

One thing looks clear. The pressure on global supply chains will not ease. As Huawei refines its alternative path, TSMC accelerates its own roadmap. Equipment makers weigh compliance risks against lost sales. And governments on both sides of the Pacific treat semiconductor mastery as strategic necessity. The race continues. Huawei just changed its stride.